Dynamically scheduled Cholesky factorization on multicore architectures with GPU accelerators - SAAHPC 2010

Dynamically scheduled Cholesky factorization on multicore architectures with GPU accelerators - SAAHPC 2010

Emmanuel Agullo, Cédric Augonnet, Jack Dongarra, Hatem Ltaief, Raymond Namyst, Jean Roman, Samuel Thibault, Stanimire Tomov

Abstract—Although the hardware has dramatically changed in the last few years, nodes of multicore chips augmented by Graphics Processing Units (GPUs) seem to be a trend of major importance. Previous approaches for scheduling dense linear operations on such a complex node led to high performance but at the double cost of not using the potential of all the cores and producing a static and non generic code. In this extended abstract, we present a new approach for scheduling dense linear algebra operations on multicore architectures with GPU accelerators using a dynamic scheduler capable of using the full potential of the node. We underline the benefits both in terms of programmability and performance. We illustrate our approach with a Cholesky factorization relying on cutting edge GPU and CPU kernels achieving roughly 900 Gflop/s on an eight cores node accelerated with three NVIDIA Tesla GPUs.
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Bibtex

@inproceedings{AguAugDonLtaNamRomThiTom10SAAHPC,
URL = {http://hal.inria.fr/inria-00547616/en/},
title = { {D}ynamically scheduled {C}holesky factorization on multicore architectures with {GPU} accelerators.},
author = {{A}gullo, {E}mmanuel and {A}ugonnet, {C}{'e}dric and {D}ongarra, {J}ack and {L}taief, {H}atem and {N}amyst, {R}aymond and {R}oman, {J}ean and {T}hibault, {S}amuel and {T}omov, {S}tanimire},
language = {{A}nglais},
booktitle = {{S}ymposium on {A}pplication {A}ccelerators in {H}igh {P}erformance {C}omputing ({SAAHPC}) },
address = {{K}noxville, USA },
audience = {internationale },
month = {07},
year = {2010},
URL = {http://hal.inria.fr/inria-00547616},
keywords = {StarPU},
}